...let the train take the strain ...look...look away...relax...think...
IDE and fl oppy controllers
GPIO and SRAM controllers
Binary I/O
Graphics, Ethernet, etc.
Other functions can be developed on request
and combined with third-party IP cores.
FPGA Organization
IP cores are realized in VHDL on the standard
Wishbone bus. As the software views the FPGA
as only one PCI device, MEN has defi ned a
ROM memory structure that allows recog-
nition of the individual functions and their
resources and subsequent driver design.
Also, loading of the FPGA is done dynamically.
After power-on the FPGA is not loaded, all
pins are tri-state. The CPU‘s BIOS now fi rst
loads the FPGA. To do this a part of the BIOS
Flash memory was reserved. Common BIOS
Flash update mechanisms can fl ash the
memory contents and thus change I/O func-
tionality. And even when the operating
system has booted up, the FPGA can be
reprogrammed at any time. For PowerPC
®
platforms, for instance, you could fi rst load
basic functionality through BIOS, e. g. a CAN
controller. The operating system can then
add the remaining functionality depending
on the device confi guration.
Standard FPGA Development
Platform
The F206N is a 3U CompactPCI
®
slave card
with an on-board Altera
®
Cyclone™ FPGA
(144,000 gates) and the integrated Nios
®
II
soft processor. It is designed for fi nal use in
volume in an application and it acts at the
same time as the standard FPGA development
platform for this application:
32 MB SDRAM, 2 MB Flash
Flexible FPGA-Flash structure
Open platform FPGA development package
Support of Wishbone and Avalon
®
bus
-40 to +85°C with qualifi ed components
FPGAs in Automated Train
Operation
In this application the control and monitoring
system provides a response channel that allows
the permanent transmission of status data of
the vehicles back to the control center.
The redundant 3U CompactPCI
®
computer
systems consist of standard Pentium
®
III based
single-board computers. They feature a low-
vol tage Celeron
®
with 650 MHz clock fre-
quen cy, two Fast Ethernet and two serial
ports. The serial interfaces and an additonal
watchdog are implemented as IP cores in the
on-board FPGA.
The second card in the system comes with
eight additional serial interfaces which are all
realized in FPGA and which work in asyn-
chronous RS422 mode and in synchronous
HDLC mode.
Another card delivers the remaining I/Os
required in the system, consisting of digital
I/O channels, analog outputs, counter pulses,
a radar sensor to pick up data from the route
sensors and interrupt inputs.
All these functions are again confi gured in
the on-board FPGA.
EN 50155 in Development
and Production
Flexible and Future-Safe
with FPGA Technology
System Solutions and
Packaging Technology
Standard Computer Boards
I/O Boards for Control and
Instrumentation
Fieldbus Solutions
Traffi c Management Systems
Passenger Information Systems
Application Samples
Short Product Overview
References
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35
38
(36 stránky)
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